数字化，高分辨率，高帧频一直是图像系统的发展趋势，这给图像传感器芯片的

数字化，高分辨率，高帧频一直是图像系统的发展趋势，这给图像传感器芯片的数据输出速率提出了更高的要求。大面阵的图像传感器芯片面积大，信号走线较长，寄生电容

大，单帧数据量大，在高帧频的应用中很难实现单路的高速数据输出。

通常采用多路低速并行数据输出的方式实现大数据量的输出，但这种方式需要多个芯片管脚，不方便使用；也可采用传统的移位寄存器单路输出的方式单路输出数据，但这种

方法的功耗过大，让人无法接受；还可以采用SRAM对数据进行缓存和读出，但SRAM的设计难度大，且阵列型图像传感芯片物理实现中，单排长条状的SRAM单元布局约束，使得

这种方法并不能满足高速数据读出的要求。

本文设计了一种用于数字传感器芯片中进行高速数据输出的电路结构，将大量的并行数据分组，各组数据串行连接，分组进行输出，各组数据公用一条输出数据线，工作时每

次选中一组数据并通过输出线将数据串行输出，如此依次分别选中各组数据并进行输出，从而实现数据的单线串行化输出；对寄生很大的输出线采用电流驱动的方式，在输出

线的端接电阻上生成低电压摆幅信号，再用放大器将低压信号恢复成全摆幅信号，从而实现数据的高速输出。仿真结果表明，本文所提出的电路结构可达到单路1Gbit/Sec的数

据输出速度，在相同的输出速率下，其功耗仅为传统以为寄存器方式单路输出结构功耗的N分之一，并且，图像传感器阵列越大，其功耗优势越明显。

結果 (英文) 1:

Digital, high resolution, high frame frequency is always the development trend of the system, this image sensor chip of data output rate put forward higher requirements. Large area of large plane array image sensor chip, a long signal alignment, parasitic capacitanceLarge, single frame of large amount of data, is difficult to achieve in the applications of high frame rate single channel high speed data output.Multi-channel low-speed parallel data output mode is usually used to achieve the output of large amounts of data, but this approach requires multiple chip pins, inconvenient to use; also can use traditional single single output the data output shift register, but thisWay too much power, make it impossible to accept; can also use cache data SRAM and read out, but the design of the SRAM is difficult, and array-type image sensor chip physical implementations, single-row Strip SRAM cell layout constraints, makingThis approach does not meet the requirements of high-speed data readout.Designed for high-speed data output of the digital sensor circuit structure, a large number of parallel data block, each set of data to the serial connection, grouped output data in each group share a single output data line at workSelect a set of data and output data to a serial output, and output are individually selected for each group, so as to realize the single serial data output; output of the parasitic great line by current-driven approaches in the outputGenerated on the line terminating resistor low voltage swing signal, to make low voltage signal recovery amplifiers help swing signals, in order to achieve high-speed data output. Simulation results show that this circuit can reach single 1Gbit/SecAccording to output speed at the same output rate, the power consumption of conventional thought the register n to one single output structure power consumption, and the larger image sensor array, its power advantage is more obvious.

結果 (英文) 3:

Digital, high resolution, high frame rate has been the development trend of image system, which put forward higher demands to the image sensor chip data output rate. Large area array image sensor chip area is large, the signal line is longer, the parasitic capacitance

, single frame of large amount of data, the application of high frame rate is very difficult to realize high speed data output single road. The output

usually adopts multiple low-speed parallel data output mode to realize a large amount of data, but this way needs a plurality of chip pins, the use is not convenient; also can adopt the traditional mode shift register single output single output data, but the power consumption of the

method is too large,Unacceptable; can also use SRAM cache and read the data, but the difficulty of design of SRAM, and the array type image sensing chip in physical implementation, SRAM cell layout constraints single platoon strip, making the

this method does not satisfy the requirements of high speed data readout.

This paper designs a kind of circuit structure for high-speed data output digital sensor chip, a large number of parallel data packets, each packet of data serial connection, each data output, an output data line, work every

time to select a group of data through an output line will serial data output,So are selected each data and output, thereby realizing mongline serial output data; on the output line parasitic large current driving way, in the output

line terminating resistor formed on the low voltage swing signal, and then the amplifier will low voltage signal recovery help swing signal, so as to realize the high speed output data. The simulation results show that, the circuit structure is proposed in this paper can achieve single 1Gbit/Sec number

according to the output speed, the output speed is same, its power consumption is only one-third of the traditional thought, register mode single output structure of power N and image sensor array, the greater the power, the more obvious advantage.